There are difficulties in scaling FET and MOS transistors to ever small dimensions. These problems, related to diminished channel length, are known as “short channel effects”.
Some MOS type submicron devices can be made sub-micron size without a problem because short channel effects are not important in some applications. On the other hand, other devices require larger channels and gates because short channel effects are very important but manufacturing rules frequently do not allow any drastic size differences, or scaling, of devices. For memory devices, for example, built in large arrays, infinite output impedance is critical for operation low power, for retaining charge, and for greater device reliability. What is needed are scalable devices, i.e., the ability to manufacture devices having channels and gates of any desired size under variable manufacturing rules.
Vertical transistor geometries are known. Such devices have a channel whose length can be adjusted. For example, U.S. Pat. No. 6,313,487 shows a transistor structure with a substrate containing a drain electrode, a source region in a silicon layer over the substrate and a channel vertically therebetween. A floating gate and a control gate overlie the channel in a spaced relation. By controlling the thickness of layers between source and drain, channel length can be controlled.
U.S. Pat. No. 6,580,124 is a device wherein a body of semiconducting material is deposited on a substrate. This is termed a “channel body” because the channel exists between vertically spaced source and drain electrodes. The device features two channels at different vertical orientations so that two charge storage regions can be formed using charge storage elements and control gates abutting the vertical channels.
One of the problems encountered in building vertical transistors is that contact must be made with lateral faces of the device, typically the gate controlling the channel. If all contacts cannot fit within the active area of the device, then valuable wafer space is lost.
An object of the invention was to devise a vertical MOS transistor with a scalable geometry with a horizontal or planar array of contacts.